Blueprint

The compute module 0

This is a low-cost single board computer that carries the H3 CPU. Capable of booting Linux & Android with 512 MiB of RAM and WiFi support.

Created by Cyao Cyao 🚀

Tier 1

1470 views

9 followers

Timeline

chakrish.ish chakrish.ish gave kudos to The compute module 0 ago

:0 wow

wizard maddy (manni) wizard maddy (manni) 🚀 gave kudos to The compute module 0 ago

meow best hardware cat of hc fr fr

nalijar201034 nalijar201034 gave kudos to The compute module 0 ago

This is an amazing project

Cyao Cyao 🚀 added to the journal ago

Ordered the PCB

I'll need to reverse journal a bit

First I did a few new fixes to the design, like shrinking the inner pwr plane and improving the routing, mitigating power splits and improving signal integrity. Also re-checked the entire design, like my power H3 custom symbol and footprint.

image

image

Took quite a bit of time as I had to well re-check everything

Also bom optimized a ton! Merged resistors, caps and more

lowpolyphosphorus lowpolyphosphorus gave kudos to The compute module 0 ago

board looks just like a Raspberry Pi B but with usb c, cool project

krunch krunch 🚀 gave kudos to The compute module 0 ago

fancy

Simha Saraswati Simha Saraswati gave kudos to The compute module 0 ago

that is so cool

m0.hid m0.hid gave kudos to The compute module 0 ago

this looks cool

CAN CAN ⚡🚀 approved The compute module 0 ago

Tier approved: 1

Grant approved: $403.00

Cyao Cyao 🚀 submitted The compute module 0 for review ago

Tanook Tanook 🚀 requested changes for The compute module 0 ago

err u linked https://github.com/cheyao/icepi-zero not your new project...

Cyao Cyao 🚀 submitted The compute module 0 for review ago

Cyao Cyao 🚀 added to the journal ago

Finished da PCB

Soo... I finished it! Routed out some of the gpio, but some others are like plain stuck inside so I'm not even gonna bother. Routing em out will likely require a total respin.

image

image

Cyao Cyao 🚀 added to the journal ago

Almost finished...

Soooo,,,, yep, routed all this out,,,
5k tracks, 1.4k pads and ~600 vias
Now only some ground stitching, 2 leds and GPIO left... And need to do a small pass on reference continuities...

image

Cyao Cyao 🚀 added to the journal ago

Placed buck converters and routed

Did a lot more routing, placed buck converters, improved layout and all kinds of routing. Nothing more to say so fuck this stupid word count that is stupid

image

Cyao Cyao 🚀 added to the journal ago

More routing

Routed even more of the board and some of the DCDC converters. Notably the EPHY and SD card connector, but also some other stuff that you see on the pcb

image

Cyao Cyao 🚀 added to the journal ago

Decoupling on pcb!

Decoupled a bunch, improved schematic & also calculated the inductor values. I also switched around the models of the dcdc converters to get better inductors.

image

Cyao Cyao 🚀 added to the journal ago

Decoupled CPU

Added quite a bit of decoupling and started to route things out. The stuff around the CPU is truly starting to take shape. Final product should be done soon.
image

image

Tanook Tanook 🚀 gave kudos to The compute module 0 ago

looks nice

Cyao Cyao 🚀 added to the journal ago

Drew large part of DC DC converters

Drew the most of the power lanes. Also drew a power distribution schematic for easier viewing. This was hard to determine tbh, still got quite some work.

image

image

Cyao Cyao 🚀 added to the journal ago

Layed out PCB

Added some GPIO, Audio I/O and layed out the board for future reference, only power and a bit more of drawing the H3 symbol left and I'll start rotuign

imageimageimage

Cyao Cyao 🚀 added to the journal ago

Drew eMMC, sdcard and schematic

Drew eMMC & more H3 symbol, sdcard footprint and routed out a bit more of the schematic, this took quite a while ugh...... I'm tired now, but this gotta continue

image
image
image
image

Cyao Cyao 🚀 added to the journal ago

Expanded RF and added tvs

Expanded the RF section by a bit

image

Also added some TVS diodes

image

A lot of the symbols r custom symbols that I drew by myself in the symbol editor of kicad ide.

Cyao Cyao 🚀 added to the journal ago

Decoupled ddr3 and drew foorprint

Placed decoupling caps for my DDR3 memory:

image

Also drew a custom RJ45 ethernet connector footprint for future use.

image

Nothing more, did this tonight after school.

Cyao Cyao 🚀 added to the journal ago

Drew USB schematic

Drew USB schematic with all the ports needed for this compute module that I am making . Also had to draw a few more custom footprints and symbols ugh.

image

Cyao Cyao 🚀 added to the journal ago

Re-match DDR3 for the 3rd time

Re-matched the traces yet again
This time moved L3 to the back again (Or else the clock trace won't work out) and changed up some data pairs for generally cleaner routing

image

Cyao Cyao 🚀 added to the journal ago

Rerouted DDR3

Soooo I've done it,,, re-routed the fucking entire DDR3 to follow the 3W rule and generally become better. L4 also got swapped with L3 for better things

image

Cyao Cyao 🚀 added to the journal ago

Drew more symbols and footprints

Sooo,,, drew some more custom symbols and footprints, drew schematic for gpdi and wifi and bluetooth. Quite easy imo but took some time to do this....

image
image
image
image
image

Cyao Cyao 🚀 added to the journal ago

Added support for 1GB of RAM

Added support for 1GB of ram and length tuned a few missed trace. Nothing else to say that's why I hate this word count ugh. Like common just get to the thing

image

Cyao Cyao 🚀 added to the journal ago

Length matched DDR3

Sooo guess what, the DDR3 is routed and length matched! Am proud of the design and happy about what I did. Nothing else to say in this stupid devloge.

image

Cyao Cyao 🚀 added to the journal ago

Continued to route DDR3

Continued to route DDR3, routed out a lot of data lines and all of the address lines. Currently it's also looking a lot cleaner than what I hade before this.

image

Cyao Cyao 🚀 added to the journal ago

Routing DDR3

Doin' more work! Routing the DDR3 right now and it's becoming soo much cleaner. Wanted to do a dual rank ddr but oh well one step at a time. This is now way harder than FPGAs as well yk the pins r set

image

Cyao Cyao 🚀 added to the journal ago

Drew DDR3 and started routing

Drew DDR3 schematic and started routing it! Goal is 4 layer pcb w/ low cost. Not much to explain here if you need more info go to google or eevblog forum.

image

image

Cyao Cyao 🚀 added to the journal ago

Designed custom H3 symbol

So, I've made a custom H3 symbol & footprint (First part of it). Took quite some time as I needed to manually place all the pins on the thingy so I had to do the thing.

image

image

Cyao Cyao 🚀 started The compute module 0 ago