The compute module 0
This is a low-cost single board computer that carries the H3 CPU. Capable of booting Linux & Android with 512 MiB of RAM and WiFi support.
Created by
chengyin.yao ๐
Tier 1
3460 views
32 followers
forgamingy227
gave kudos to The compute module 0 ago
you sure your a teenage ? because wow really wow
Kobi Rowlinson
gave kudos to The compute module 0 ago
bro make a raspberry pi impressive๐ฎ
NullByte
gave kudos to The compute module 0 ago
cool!
shaikshahirsiddiqui
gave kudos to The compute module 0 ago
DAmnnnNNN
Tanuki โก๐
gave kudos to The compute module 0 ago
whoa this is so cool
thamizhmalathi81
gave kudos to The compute module 0 ago
No words ... just pure skills โค๏ธโ๐ฅโค๏ธโ๐ฅ๐ฏ
martiksimonian27
gave kudos to The compute module 0 ago
My level of intelligence is far too low to understand what level of impressive this actually is.
housey2k
gave kudos to The compute module 0 ago
Damn this is awesome! I always thought that making a SBC was something far from reach for a single person. I'm genuinely impressed.
alexren โก๐
approved The compute module 0 ago
Tickets awarded: 120 tickets
Tier: 1
hi!! this project is actually insane - im docking off 8 hours because you're self reporting working 13/hr a day for 2 days straight, and also debugging for 11 hours without really going that far into what took so long / learnings from it.
chengyin.yao ๐
submitted The compute module 0 for review ago
chengyin.yao ๐
added to the journal ago
Finished the firmware


Welp so I did a lot more debugging... Soldered on crystal oscillators on multiple boards, did some reflow soldering and then discovered I actually scrambled a ram...

I've also made a custom USB cable and finally got it to show up as a fel device. Then I dug hard into allwinner's software, which was a goddamn mess. Had to download official (?) tools from 3rd parties. But I got the ram working!
Then after a lot of other work and kernel compiling, I got linux & android running on the board:


wasted two whole days on this....
chengyin.yao ๐
added to the journal ago
Debugging
Welp I've been debugging quite a bit:

Somehow it wasn't booting up, and I spent way too long looking at the schematic and probing around... Welp turns out that somehow I messed up the crystal's CL and it wasn't oscillating. So I bridged on a crystal oscillator

Now the usb is being detected but well it isn't correctly being enumerated :c
avidgamer
gave kudos to The compute module 0 ago
:0 wow
wizard maddy (manni) ๐
gave kudos to The compute module 0 ago
meow best hardware cat of hc fr fr
Naytik
gave kudos to The compute module 0 ago
This is an amazing project
chengyin.yao ๐
added to the journal ago
Ordered the PCB
I'll need to reverse journal a bit
First I did a few new fixes to the design, like shrinking the inner pwr plane and improving the routing, mitigating power splits and improving signal integrity. Also re-checked the entire design, like my power H3 custom symbol and footprint.


Took quite a bit of time as I had to well re-check everything
Also bom optimized a ton! Merged resistors, caps and more
lowpolyphosphorus
gave kudos to The compute module 0 ago
board looks just like a Raspberry Pi B but with usb c, cool project
krunch ๐
gave kudos to The compute module 0 ago
fancy
Simha Saraswati
gave kudos to The compute module 0 ago
that is so cool
m0.hid โก
gave kudos to The compute module 0 ago
this looks cool
CAN โก๐
approved The compute module 0 ago
Tier approved: 1
Grant approved: $403.00
chengyin.yao ๐
submitted The compute module 0 for review ago
Tanuki โก๐
requested changes for The compute module 0 ago
err u linked https://github.com/cheyao/icepi-zero not your new project...
chengyin.yao ๐
submitted The compute module 0 for review ago
chengyin.yao ๐
added to the journal ago
Finished da PCB
Soo... I finished it! Routed out some of the gpio, but some others are like plain stuck inside so I'm not even gonna bother. Routing em out will likely require a total respin.


chengyin.yao ๐
added to the journal ago
Almost finished...
Soooo,,,, yep, routed all this out,,,
5k tracks, 1.4k pads and ~600 vias
Now only some ground stitching, 2 leds and GPIO left... And need to do a small pass on reference continuities...

chengyin.yao ๐
added to the journal ago
Placed buck converters and routed
Did a lot more routing, placed buck converters, improved layout and all kinds of routing. Nothing more to say so fuck this stupid word count that is stupid

chengyin.yao ๐
added to the journal ago
More routing
Routed even more of the board and some of the DCDC converters. Notably the EPHY and SD card connector, but also some other stuff that you see on the pcb

chengyin.yao ๐
added to the journal ago
Decoupling on pcb!
Decoupled a bunch, improved schematic & also calculated the inductor values. I also switched around the models of the dcdc converters to get better inductors.

chengyin.yao ๐
added to the journal ago
Decoupled CPU
Added quite a bit of decoupling and started to route things out. The stuff around the CPU is truly starting to take shape. Final product should be done soon.


Tanuki โก๐
gave kudos to The compute module 0 ago
looks nice
chengyin.yao ๐
added to the journal ago
Drew large part of DC DC converters
Drew the most of the power lanes. Also drew a power distribution schematic for easier viewing. This was hard to determine tbh, still got quite some work.


chengyin.yao ๐
added to the journal ago
Layed out PCB
Added some GPIO, Audio I/O and layed out the board for future reference, only power and a bit more of drawing the H3 symbol left and I'll start rotuign



chengyin.yao ๐
added to the journal ago
Drew eMMC, sdcard and schematic
Drew eMMC & more H3 symbol, sdcard footprint and routed out a bit more of the schematic, this took quite a while ugh...... I'm tired now, but this gotta continue




chengyin.yao ๐
added to the journal ago
Expanded RF and added tvs
Expanded the RF section by a bit

Also added some TVS diodes

A lot of the symbols r custom symbols that I drew by myself in the symbol editor of kicad ide.
chengyin.yao ๐
added to the journal ago
Decoupled ddr3 and drew foorprint
Placed decoupling caps for my DDR3 memory:

Also drew a custom RJ45 ethernet connector footprint for future use.

Nothing more, did this tonight after school.
chengyin.yao ๐
added to the journal ago
Drew USB schematic
Drew USB schematic with all the ports needed for this compute module that I am making . Also had to draw a few more custom footprints and symbols ugh.

chengyin.yao ๐
added to the journal ago
Re-match DDR3 for the 3rd time
Re-matched the traces yet again
This time moved L3 to the back again (Or else the clock trace won't work out) and changed up some data pairs for generally cleaner routing

chengyin.yao ๐
added to the journal ago
Rerouted DDR3
Soooo I've done it,,, re-routed the fucking entire DDR3 to follow the 3W rule and generally become better. L4 also got swapped with L3 for better things

chengyin.yao ๐
added to the journal ago
Drew more symbols and footprints
Sooo,,, drew some more custom symbols and footprints, drew schematic for gpdi and wifi and bluetooth. Quite easy imo but took some time to do this....





chengyin.yao ๐
added to the journal ago
Added support for 1GB of RAM
Added support for 1GB of ram and length tuned a few missed trace. Nothing else to say that's why I hate this word count ugh. Like common just get to the thing

chengyin.yao ๐
added to the journal ago
Length matched DDR3
Sooo guess what, the DDR3 is routed and length matched! Am proud of the design and happy about what I did. Nothing else to say in this stupid devloge.

chengyin.yao ๐
added to the journal ago
Continued to route DDR3
Continued to route DDR3, routed out a lot of data lines and all of the address lines. Currently it's also looking a lot cleaner than what I hade before this.

chengyin.yao ๐
added to the journal ago
Routing DDR3
Doin' more work! Routing the DDR3 right now and it's becoming soo much cleaner. Wanted to do a dual rank ddr but oh well one step at a time. This is now way harder than FPGAs as well yk the pins r set

chengyin.yao ๐
added to the journal ago
Drew DDR3 and started routing
Drew DDR3 schematic and started routing it! Goal is 4 layer pcb w/ low cost. Not much to explain here if you need more info go to google or eevblog forum.


chengyin.yao ๐
added to the journal ago
Designed custom H3 symbol
So, I've made a custom H3 symbol & footprint (First part of it). Took quite some time as I needed to manually place all the pins on the thingy so I had to do the thing.


chengyin.yao ๐
started The compute module 0 ago
10/28/2025 - Designed custom H3 symbol
So, I've made a custom H3 symbol & footprint (First part of it). Took quite some time as I needed to manually place all the pins on the thingy so I had to do the thing.


10/29/2025 11 AM - Drew DDR3 and started routing
Drew DDR3 schematic and started routing it! Goal is 4 layer pcb w/ low cost. Not much to explain here if you need more info go to google or eevblog forum.


10/29/2025 9 PM - Routing DDR3
Doin' more work! Routing the DDR3 right now and it's becoming soo much cleaner. Wanted to do a dual rank ddr but oh well one step at a time. This is now way harder than FPGAs as well yk the pins r set

10/31/2025 4 PM - Continued to route DDR3
Continued to route DDR3, routed out a lot of data lines and all of the address lines. Currently it's also looking a lot cleaner than what I hade before this.

10/31/2025 10 PM - Length matched DDR3
Sooo guess what, the DDR3 is routed and length matched! Am proud of the design and happy about what I did. Nothing else to say in this stupid devloge.
11/1/2025 - Added support for 1GB of RAM
Added support for 1GB of ram and length tuned a few missed trace. Nothing else to say that's why I hate this word count ugh. Like common just get to the thing

11/2/2025 12 PM - Drew more symbols and footprints
Sooo,,, drew some more custom symbols and footprints, drew schematic for gpdi and wifi and bluetooth. Quite easy imo but took some time to do this....





11/2/2025 6 PM - Rerouted DDR3
Soooo I've done it,,, re-routed the fucking entire DDR3 to follow the 3W rule and generally become better. L4 also got swapped with L3 for better things

11/3/2025 9 AM - Re-match DDR3 for the 3rd time
Re-matched the traces yet again
This time moved L3 to the back again (Or else the clock trace won't work out) and changed up some data pairs for generally cleaner routing

11/3/2025 9 PM - Drew USB schematic
Drew USB schematic with all the ports needed for this compute module that I am making . Also had to draw a few more custom footprints and symbols ugh.

11/4/2025 - Decoupled ddr3 and drew foorprint
Placed decoupling caps for my DDR3 memory:

Also drew a custom RJ45 ethernet connector footprint for future use.

Nothing more, did this tonight after school.
11/5/2025 - Expanded RF and added tvs
Expanded the RF section by a bit

Also added some TVS diodes

A lot of the symbols r custom symbols that I drew by myself in the symbol editor of kicad ide.
11/6/2025 - Drew eMMC, sdcard and schematic
Drew eMMC & more H3 symbol, sdcard footprint and routed out a bit more of the schematic, this took quite a while ugh...... I'm tired now, but this gotta continue




11/8/2025 - Layed out PCB
Added some GPIO, Audio I/O and layed out the board for future reference, only power and a bit more of drawing the H3 symbol left and I'll start rotuign



11/9/2025 - Drew large part of DC DC converters
Drew the most of the power lanes. Also drew a power distribution schematic for easier viewing. This was hard to determine tbh, still got quite some work.


11/10/2025 - Decoupled CPU
Added quite a bit of decoupling and started to route things out. The stuff around the CPU is truly starting to take shape. Final product should be done soon.


11/11/2025 - Decoupling on pcb!
Decoupled a bunch, improved schematic & also calculated the inductor values. I also switched around the models of the dcdc converters to get better inductors.

11/12/2025 - More routing
Routed even more of the board and some of the DCDC converters. Notably the EPHY and SD card connector, but also some other stuff that you see on the pcb

11/13/2025 - Placed buck converters and routed
Did a lot more routing, placed buck converters, improved layout and all kinds of routing. Nothing more to say so fuck this stupid word count that is stupid

11/15/2025 6 PM - Almost finished...
Soooo,,,, yep, routed all this out,,,
5k tracks, 1.4k pads and ~600 vias
Now only some ground stitching, 2 leds and GPIO left... And need to do a small pass on reference continuities...

11/15/2025 10 PM - Finished da PCB
Soo... I finished it! Routed out some of the gpio, but some others are like plain stuck inside so I'm not even gonna bother. Routing em out will likely require a total respin.


12/12/2025 - Ordered the PCB
I'll need to reverse journal a bit
First I did a few new fixes to the design, like shrinking the inner pwr plane and improving the routing, mitigating power splits and improving signal integrity. Also re-checked the entire design, like my power H3 custom symbol and footprint.


Took quite a bit of time as I had to well re-check everything
Also bom optimized a ton! Merged resistors, caps and more
12/20/2025 - Debugging
Welp I've been debugging quite a bit:

Somehow it wasn't booting up, and I spent way too long looking at the schematic and probing around... Welp turns out that somehow I messed up the crystal's CL and it wasn't oscillating. So I bridged on a crystal oscillator

Now the usb is being detected but well it isn't correctly being enumerated :c
12/22/2025 - Finished the firmware


Welp so I did a lot more debugging... Soldered on crystal oscillators on multiple boards, did some reflow soldering and then discovered I actually scrambled a ram...

I've also made a custom USB cable and finally got it to show up as a fel device. Then I dug hard into allwinner's software, which was a goddamn mess. Had to download official (?) tools from 3rd parties. But I got the ram working!
Then after a lot of other work and kernel compiling, I got linux & android running on the board:


wasted two whole days on this....