Edited PCB for price improvements

Yep so this is probably the final update before we ship this. I edited the fanout traces so that I wouldn't have to specify a stackup (100 bucks at JLC). It's still six layers and in the image, most of the traces look the same (You probably won't see the .04mm difference).

This was a great journey where I learned a bunch about high speed signal routing, component placements and just intuition in general!

Hoping this will be placed in tier one or else I'll go bankrupt!

Finished BOM + Gerbers

Hey everyone!
I recently finished the BOM and finished organizing all of the Gerbers. As per Blueprint instructions, I have uploaded all of them to the github repo, so feel free to check them out. For now I haven't uploaded all of the libraries/3d models I have used for the components, which I will do at a later date.
Next stop will be finding a suitable price for everything!

Feedback implementation + silkscreen

I got feedback from professionals from the KiCAD official server, and there were no major faults!!! Hip hip hooray lol!!!
I fixed a few things like adding more vias since they don't cost anything to add, fixing up some traces, double checking that values were correct, and adding some silkscreen so that the board looked nice/I knew what was what!

Polished up the schematic + waiting for professional review

So after last update, where I finished up the routing, this time I tried to fix up the schematic to make it look pretty for professionals to review. I sent it over to KiCAD's official server, where experienced people will look at it!

Cleaning up the schematic was ridicously annoying, as I had to move all of the dang FPGA pins around... That was a whole time with carpal tunnel...

After I get a review of my schematic + routing, I'll fix all of the errors on the next update!

Added pin headers + cleaned up routing + other QOL

I added a 40 pin header, perfect for people who want to experiment using io pins!
Added a couple of mounting holes and filleted edge cuts!
Moved a couple of components around a bit to make the design look a bit more cleaner, and messed with the traces to make them look more clean/efficent.
I may or may not change the FPGA decoupling caps later, as it is a bit messyish/

Finished routing everything!!!!

It's here!!! The finished routed version of the Minty board!!!
All I did were a few minor changes, such as cleaning up vias, improving traces, connecting GND + Power pins.
Not too much, but it was definitely the more annoying portion...
After I clean up my schematic and get reviews from professionals, I should be able to ship the board!!!

Finished routing microSD (for real this time)

So I finished routing the microSD component, and pin mapped to the preferred pins. I think that this will be the last major feature, and that I won't add any more... (maybe)...
I still need to connect a few power pins, so I will do some revisions + add a few LEDs tommorow!
Otherwise the board should be almost complete!!!

Routed HDMI connector + schematic

Okay before I start, I just want say. Cramming a HDMI connector into BGA pads is not fun. At all.
I basically removed the entire microsd for now, since HDMI had to be closer to the FPGA cuz signal priority + high speed signals etc etc...
I'll probably put microSD at a later time, maybe above the HDMI connector.
I still have some space for one more cool thing, so I need more ideas lol!!!

Finished routing microSD + QOL improvements!

Heyo guys, I finished routing all of the microSD pins!!!
This part was a bit easy, since microSD doesn't need too much strict requirements, so I routed the traces cleanly, and made sure that they were decently length matchedish.
I was thinking about moving the USB, and moving a few components to make the board smaller, but I did not want to risk getting too much interference (two high speed signals right next to each other (DDR3 + USB is not a good combo)...
I fixed up some traces, as I forgot to send 5V traces to the power regulators. I used a simple copper pour, (maybe three different copper pours on one layer is okay??) and did multiple vias + thick traces as the current was pretty big.

Created/Routed osc schematic + optimization

I finally added the 100 MHz oscillator. I chose the ECS-3225MVQ-1000-CN-TR, since it was fairly cheap, but also reputable. The oscillation waves were very clean, suitable for my DDR3 clock references!
I also optimized my power supply placement a bit, as I realized I had just enough space to squeeze in my AMS-1117 (3.3V fixed).
The design looked more clean overall!

I fixed some traces as well, opting for a more professional and efficient route.

If you read this, I would appreciate it if you could DM me some ideas about what I should add next, like sensors or anything really cool!

Finished routing all of the power yahoo

As you can see in the picture, I finished routing and placing the linear regulator modules. It feels a bit unoptimized to me, but for now its pretty functional and it works!
I hate how there is empty space there, but it is a "oh well can't do much about it" moment.
I'll probably clean up the vias since they look uneven, but overall a decent idea.
I forgot about the clock, so I have to make the schematic for that, but that is easy!!!
I feel like I need more of a bang on the board, so tomorrow will just be tidying up and thoughts!

Revised power supply/regulation + routing (TY TO CYAO!!!)

After talking with Cyao, a neighborhood FPGA expert, I realized that I could have optimized my component selection!
Taking into account his feedback, I completely changed all of the TLV series fixed linear regulators to TPS series linear adjustable regulators. It added a few more discrete components, but it saved me a ton of money on JLC's extended part reel fee!
I didn't add vias to the GND pads of the modules, since I still had to figure out where I would place them, and how I would link them up to the FPGA.

Placement + Routing of Caps + Power regulators

For this journal entry, I finished doing all of the decoupling caps on the FPGA. Standard rule of 1 100n cap per power pin and a few 10u spread out.
The decoupling cap layout is a bit messy, but it is what it is :///
I also did the routing of the power supply regulators. I didn't fully connect them to the FPGA/power plane yet, but it should just be a couple of copper pours and traces away!

Routed USB + Flash Memory

I finished routing all of the USB and flash memory components!!!
I didn't attach a picture, but I mapped all of the relevant usb/flash pins to FPGA GPIOs. I tried my best to fanout the BGA in a way that saved most of the GPIO pins.
Remembering to keep 90 differential pair impedance for the USB traces, and thick traces for the power traces!
I still need to do power, which might take alot of time :pensive:!

Finished DDR3 Routing + USB Serial Schema

So I think I violated some common conventions of routing but here I am!!!
Sadly I had to do via on pad for the DDR3 ram power, since they are decouplings and I can't place them too far...
After that nightmare was over, I started on the USB + USB serial converter schematic since it was a pretty important portion to me! I took a look at the datasheet, and pin mapped relevantly!
I also did the microSD schematic since it was decently easy, and I was really familiar with it!
I'll probably start routing a bit later during the day!

Routed the DDR3 RAM (DID NOT DO POWER YET)

Keeping in mind the strict impedance (50 ohms) and length matching (clock + data + address traces), I started and finished the routing today. (This should be the most up to date thing for now).
I put some 33 ohm resistors to improve ringing resistance, and provide a termination point for the clock signals. Address did not need resistors, even though they are "recommended" as the trace lengths were under 1 inch!
I had to spam skew tuning because most traces had to be length matches and my eyes just see squiggly lines....
But yeah this was worth the effort and tomorrow I have to suffer doing power (backside of the board...)

Finished RAM schematic + thoughts about potential routing.

Building off of the RAM module that I chose, I took a look at the reference manual/datasheet, and mapped the pins to the particular FPGA pin that was needed!
I also added a bunch of decoupling caps since I needed a really stable and clean power source to the RAM.
Address and Data pins did not have a specific pin to map to, so I assigned it in a logical way that would make it the most easiest to route.
I also made sure to make a mental note to do impedance (50 ohms) and length matching.

Finished flash memory + JTAG

Added net labels and connected the pins of the flash memory (did not do WP or RESET as they don't have specific FPGA pins).
Initializing the JTAG was easy, as they just needed a couple of pullups/pulldowns!
I also decided on the RAM module that I wanted to use, which was the MT41J128M16JT-125_KTR. This is a 2GB DDR3 memory, for only ~$3, which is actually pretty affordable!

Started the FPGA schematic + power source + flash memory!

Added decoupling capacitors for VCCIO, VCC and a filtering system for VCCAUX.
Tied all relevant VSS/VSSQ pins to ground, as per standard practice.
Decided on components for the power source, and chose to use the AMS1117 (Fixed), for the main power supply, and then various TLV713xxPDBV modules for smaller voltage rails (DDR RAM + FPGA).
Chose the W25Q128JVS, as this was a flash that was supported by the ECP5.