Blueprint

Devboard

A RP2040 devboard.

Created by Elijah Spitzer Elijah Spitzer

Tier 3

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CAN CAN ⚡🚀 approved Devboard ago

Tier approved: 3

Grant approved: $42.00

If you can, please only get 2 PCBA

Elijah Spitzer Elijah Spitzer submitted Devboard for review ago

Elijah Spitzer Elijah Spitzer added to the journal ago

Finished the PCB!

The PCB was a crazy challenge. If you look in the SS at the bottom you can see that I did end up finally finishing it with 0 DRC errors!

From my last journal I continued work on the PCB, creating silly routing and most of the time having no clue what I was doing:
Screenshot 2025-11-17 at 8.33.02 PM
But from talking with Kai Pereira through the entire process I learned more and more. One of the biggest things I learned was about GND via's, which were kind of confusing, but once I figured them out are really easy now.

On Saturday, November 22, I decided to take all my new routing experience, and now that I actually knew what was going on I redid everything ( excluding the power/data as that has to be very exact so that all the data gets to the same location at the exact same time and is incredibly difficult to do ).

As you can see in this screenshot, because I understood how stuff worked my part placement was much better. On Saturday I also got every single part routed ( excluding GPIO, Power, and Special ones )
Screenshot 2025-11-22 at 9.36.48 PM

On Sunday I continued working on routing and got the large majority of it done, there were just a few things that needed to be finished, but I ran out of time.

Screenshot 2025-11-23 at 4.40.16 PM

Today, November 25th, I finished routing by adding the ground layer, and touching up the last traces.

Screenshot 2025-11-25 at 8.23.52 PM

Now getting everything routed in a clean, and useable manner, is a difficult thing but its only part of it. I now was left with probably around 60 errors which I needed to solve.

Some text variables were undeclared, which I deleted as I didn't need them.

Kicad had a really high trace clearance rate at 2mm when JLCPCB is exact up to .16mm at the highest ( so I kept it here even though it said they could go down to .1mm just to be same ). This removed most of the trace clearance issues, and the last 3 I just routed with a higher clearance to fix those issues.

For the "thermal relief connection to zone incomplete" errors I had to do some research and talked with Kai Pereira for help. This was fixed by modifying my ground layer properties to leave me with 7 issues, which I manually routed to a new GND via, that I had learned how to do earlier.

All that was left was adding in some text to make it truly mine and then I had finished it!

Screenshot 2025-11-25 at 9.14.55 PM

( BTW regarding the 15 hours, I timed this through Slack, I sent a message when I started and sent one when I finished so I know this time is like 99% accurate. )

Elijah Spitzer Elijah Spitzer added to the journal ago

Finished the schematic, started on the PCB.

Schematic

I had no problems putting together the schematic using help from Kai Pereira's Devboard article. When I shared it for pier review no one had any issues with it. Kai Pereira went with the easier MCP1700 for power distortion ( 5v -> 3.3v ) because it was smaller. I challenged myself by using the NCP1700 which can handle more power, but is much larger.
Screenshot 2025-11-16 at 7.51.57 PM

PCB

I also started work on the PCB, Kai helped me with tuning as the USB-C positive and negative traces both have to be the exact same length so there isn't issues with data / power transfer, which was very difficult. Tomorrow my plan is to continue working on the PCB.
Screenshot 2025-11-16 at 7.55.51 PM

Elijah Spitzer Elijah Spitzer started Devboard ago

11/16/2025 - Finished the schematic, started on the PCB.

Schematic

I had no problems putting together the schematic using help from Kai Pereira's Devboard article. When I shared it for pier review no one had any issues with it. Kai Pereira went with the easier MCP1700 for power distortion ( 5v -> 3.3v ) because it was smaller. I challenged myself by using the NCP1700 which can handle more power, but is much larger.
Screenshot 2025-11-16 at 7.51.57 PM

PCB

I also started work on the PCB, Kai helped me with tuning as the USB-C positive and negative traces both have to be the exact same length so there isn't issues with data / power transfer, which was very difficult. Tomorrow my plan is to continue working on the PCB.
Screenshot 2025-11-16 at 7.55.51 PM

11/25/2025 - Finished the PCB!

The PCB was a crazy challenge. If you look in the SS at the bottom you can see that I did end up finally finishing it with 0 DRC errors!

From my last journal I continued work on the PCB, creating silly routing and most of the time having no clue what I was doing:
Screenshot 2025-11-17 at 8.33.02 PM
But from talking with Kai Pereira through the entire process I learned more and more. One of the biggest things I learned was about GND via's, which were kind of confusing, but once I figured them out are really easy now.

On Saturday, November 22, I decided to take all my new routing experience, and now that I actually knew what was going on I redid everything ( excluding the power/data as that has to be very exact so that all the data gets to the same location at the exact same time and is incredibly difficult to do ).

As you can see in this screenshot, because I understood how stuff worked my part placement was much better. On Saturday I also got every single part routed ( excluding GPIO, Power, and Special ones )
Screenshot 2025-11-22 at 9.36.48 PM

On Sunday I continued working on routing and got the large majority of it done, there were just a few things that needed to be finished, but I ran out of time.

Screenshot 2025-11-23 at 4.40.16 PM

Today, November 25th, I finished routing by adding the ground layer, and touching up the last traces.

Screenshot 2025-11-25 at 8.23.52 PM

Now getting everything routed in a clean, and useable manner, is a difficult thing but its only part of it. I now was left with probably around 60 errors which I needed to solve.

Some text variables were undeclared, which I deleted as I didn't need them.

Kicad had a really high trace clearance rate at 2mm when JLCPCB is exact up to .16mm at the highest ( so I kept it here even though it said they could go down to .1mm just to be same ). This removed most of the trace clearance issues, and the last 3 I just routed with a higher clearance to fix those issues.

For the "thermal relief connection to zone incomplete" errors I had to do some research and talked with Kai Pereira for help. This was fixed by modifying my ground layer properties to leave me with 7 issues, which I manually routed to a new GND via, that I had learned how to do earlier.

All that was left was adding in some text to make it truly mine and then I had finished it!

Screenshot 2025-11-25 at 9.14.55 PM

( BTW regarding the 15 hours, I timed this through Slack, I sent a message when I started and sent one when I finished so I know this time is like 99% accurate. )