Rerouting

This somewhat of a better routing attempt that I did. It's still a bit messy, and it has some issues. I'll probably redo most of routing here, although four layers does seem a bit tricky to do...

Routed the Ethernet Transceiver

After creating the schematic, my next task was to route the IC onto the CPU. Since the pin functions were already mapped out, I didn't have to go through much iterations on pin function mapping, which saved alot of time.

However since the BGA pins were quite dense, it was a bit annoying to fanout all of the pins (the columns/rows sit right next to each other).

I put most of the 1/0 status signal pullups/pulldowns on the other side of the board, as well as most decoupling caps to save space, and to ensure that the return/accepting path was quick.

Finished the RGMII Ethernet Transceiver Schematic

For this journal entry, I'll be talking a bit on how I made this design. After taking a look at Realtek's datasheets, most of the CPU pins were perfectly mapped out, and had a dedicated function for Ethernet RGMII, which made everything a whole lot easier.

A couple of pullups and pulldowns were needed in order to make sure that the signal was either clean, or was at a 0/1 state for certain settings.

Thankfully nothing was differentially required, but strict length and impedance matching was needed, which I will keep in mind when routing this IC.

Routed the EMMC!

After making the schematic, I just was left with all of the routing. The EMMC had only a few pins, so it was decently easy to route. I still had to impedance and length match the data and clock traces, but it was chill (only 8 pins to group together).

I revised my routing a couple of times, until I got the most efficient way that won't cover the other pins that I need to fanout.

I placed my decoupling caps and pullup resistors in a nearby area, usually on top or very close to the pins.

Next, I'll be tackling the ethernet transreciever!

Added EMMC storage!

I started off this session by researching about the types of memory commonly used in compute modules. It seemed that EMMC was the most cheapest, but efficient type!

I checked the specs of my CPU, and saw that it supported the 5.1 EMMC interface, so I inputted these parameters into LCSC.
A couple of brands came up, most notably Sandisk and SAMSUNG. I opted for SAMSUNG, since it was a bit more cost efficient, and it was extremely reputable.
After searching a bit for the symbol and footprint, Snapmagic had the exact product, which was super duper great!

I just checked the datasheet, linked up pins, added needed discrete components, etc, etc.

Rerouted RAM

It's been around a week since the last update, I was super duper swamped with work. Anyways, I cleaned up some the of the routing, and added two more layers, as I wanted a really clean and concise layer for the differential pairs!

I had to move a couple of traces around, but there weren't much changes.

Added RAM decoupling caps

Yeah so I was out the whole day so heres my progress...
I had to squeeze a lot of the decoupling caps onto the RAM since it has a absurdly crazy amount of power pins. Most of the caps are on the back since they allow for the shortest return path.
A lot, and I mean alot of via in pad was used...
I had the signal traces from the address and byte lines, which made it annoying to fit the caps (less than 0.07mm spacing), so some of the caps are a bit far away...
Alright tomorrow I plan to add the decoupling caps to the processor, and start on the power section schematic.
P.S a total of 40 decoupling caps were used....

I have prayed to the BGA gods and they have answered!!!

Yes.
I finished the RAM routing.
My back hurts.
Okay so since there need to be detail...
I routed the rest of the Address and byte lines, as long as the clock lines. The processor is really iffy since the BGA pins are all over the place, so I had to really use the three layers wisely. My clock traces are 33mm, which is absolutely crazy...
I tried my best to length match the groups (bytes and address) and I achieved a max skew of +-.5mm, which is actually pretty good!
Next, I will probably do the power section, and the decoupling caps for the RAM and RK3566.

Started the routing for LPDDR4 RAM

Hey guys! After finishing the schematic, I started routing the LPDDR4 RAM, and its safe to say that this was a real difficulty. I only routed two byte groups and it was ridiculously cramped...

I finished all of the data lines for the first two byte groups, so onto the address lines and the other byte groups :///

Finished LPDDR4 RAM schematic!

So from my goals last night, I immediately woke up to finish the RAM schematic. It was easier than anticipated, as the processor had dedicated pins for LPDDR4!
I also fixed up the schematic a bit, as it was really messy, and there was unneeded text everywhere...
I'll probably do either the eMMC portion, or the power section next, depending on my mood lol..
I will say that I haven't tried routing out everything, but it seems to be ridiculously annoying...

Started researching and schematic

I started by finding out which processor I wanted to use! This was the main component, so I decided to choose something cost effective, but also powerful! Thats when I had my eyes on the RK3566, which conveniently had a symbol and footprint already on SnapEDA!
I also researched my RAM on LCSC, when I found a beautiful SK Hynix RAM module for a extremely cheap price! 16GB of RAM, LPDDR4 at that, for less than $20!
Using my prior knowledge and skills, I checked the datasheets (I hate you Rockchip for not giving a solid datasheet) and pin mapped to the appropriate areas.
It's around 1 am right now, and I still didn't finish the RAM schematic, so I'm aiming to do the RAM and power schema tommorow!