Blueprint

LPG

A high efficiency ULP SIP GMSS, NBIoT & LTE-M nRF91 STO LTS for IOT with minimal BOM, ultra-low Iq and dedicated STO PHY (IP). It operates with an advanced LP PSM paired with an low iDRX interval RRC idle to optimize RX dBm gain using cDRX variations and variable iDRX PDCCH.

Created by chengyin.yao chengyin.yao 🚀

Tier 1

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1 follower

Tanuki Tanuki ⚡🚀 approved LPG ago

Tier approved: 1

Grant approved: $313.00

Sick PCB! I guess im a cool person lol

chengyin.yao chengyin.yao 🚀 submitted LPG for review ago

chengyin.yao chengyin.yao 🚀 added to the journal ago

Finished project

image

Made da repo, da bom and all other stuff. found GMSS ANT that I needed to use to be compliant with FCC, CE and other regulations.

Did a final pass on the PCB.

chengyin.yao chengyin.yao 🚀 added to the journal ago

Finalized PCB

image

Final product ^^

Projected ULP duration is 2 months in normal mode.

More in STO and RRC idle mode.

Signals are now all integral and return loops optimized.

chengyin.yao chengyin.yao 🚀 added to the journal ago

Compacted board

Made board a lot more compact. Picked specific parts to opt pc and iq, while minimizing surface area.

Rerouted a lot of stuff, reworked bat charge cycle.

image

chengyin.yao chengyin.yao 🚀 added to the journal ago

Continued to route

Routed the stuff.

Kept everything compact and LP. Paid attention to DRX dBm gain and minimized GMSS derivation.

Used techniques to conserve cap polarization for ULT functioning.

image

chengyin.yao chengyin.yao 🚀 added to the journal ago

Continued to route the PCB

image

Made more progress, sparing the technical details. It's just routing with ULP in consideration with EMC optimizations. I hope to get low noise on all the rails fuck this word count

chengyin.yao chengyin.yao 🚀 added to the journal ago

Started to rotue the PCB

Started to route out the PCB. Not much to say. (Well there's a ton of technical aspects but I am not in a mood to yap, I just want to remove this char counter)

image

chengyin.yao chengyin.yao 🚀 added to the journal ago

Found more components

Picked out the converter from the freaking hundreds of different converters from TI, NXP and Micro. Found this integrated inductor boost conv that has only ~300n of Iq.

Also drew other low power stuff

image

chengyin.yao chengyin.yao 🚀 added to the journal ago

Guess what, more drawing

Drew custom symbols, figured out 2nd antenna. added all kinds of modules

Calculated polarizing capacitance to optimize battery life etc.. also found new parts

image

chengyin.yao chengyin.yao 🚀 added to the journal ago

Drew core

Drew core of the schematic

Figured out the GPS antenna tuning which was goddamn obscure

image

Not much else wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww

chengyin.yao chengyin.yao 🚀 started LPG ago

1/11/2026 2 PM - Drew core

Drew core of the schematic

Figured out the GPS antenna tuning which was goddamn obscure

image

Not much else wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww

1/11/2026 8 PM - Guess what, more drawing

Drew custom symbols, figured out 2nd antenna. added all kinds of modules

Calculated polarizing capacitance to optimize battery life etc.. also found new parts

image

1/12/2026 7 PM - Found more components

Picked out the converter from the freaking hundreds of different converters from TI, NXP and Micro. Found this integrated inductor boost conv that has only ~300n of Iq.

Also drew other low power stuff

image

1/12/2026 10 PM - Started to rotue the PCB

Started to route out the PCB. Not much to say. (Well there's a ton of technical aspects but I am not in a mood to yap, I just want to remove this char counter)

image

1/13/2026 - Continued to route the PCB

image

Made more progress, sparing the technical details. It's just routing with ULP in consideration with EMC optimizations. I hope to get low noise on all the rails fuck this word count

1/14/2026 - Continued to route

Routed the stuff.

Kept everything compact and LP. Paid attention to DRX dBm gain and minimized GMSS derivation.

Used techniques to conserve cap polarization for ULT functioning.

image

1/15/2026 - Compacted board

Made board a lot more compact. Picked specific parts to opt pc and iq, while minimizing surface area.

Rerouted a lot of stuff, reworked bat charge cycle.

image

1/16/2026 4 PM - Finalized PCB

image

Final product ^^

Projected ULP duration is 2 months in normal mode.

More in STO and RRC idle mode.

Signals are now all integral and return loops optimized.

1/16/2026 5 PM - Finished project

image

Made da repo, da bom and all other stuff. found GMSS ANT that I needed to use to be compliant with FCC, CE and other regulations.

Did a final pass on the PCB.