2/18/2026 7:52 PM - did schematic (course of the last 3 days ish)

mostly just yoinked from my keyboard project schematic, however i did modify it to expose as many pins as possible since now i'm working with a 6 layer design with via-in-pad allowed
now also i did further research on chargers and stuff, and decided i will expose only vbus and vbat, even though there's a regulated out from the charger, it will be more reliable for my purposes and for the future
i will still have the charger's out point towards the 3v3 ldo for power for the nrf, since i want it to run on 3.3v logic instead of the default 1.8v
this makes it easier, as i will need no vbus on the chip, since i now changed it to be supplied via vdd, and tied vddh together so that the chip knows it will be supplied via only one power supply
no internal ldo will be active as a result because of the 3v3 external ldo, powered by the charger, which in turn can be powered by either bat or vbus power
reading datasheets and ref designs can be pain :hs:

2/18/2026 7:59 PM - started pcb

spent way too much time doing research before actually starting routing and stuff to make sure everything from caps, antenna impedence etc etc was up to spec
ofc following reference design
charger was routed
the headers are 20pin headers, but they are 0.1" wider than the pico for more internal space for me to route stuff (as i think that space will prove to be useful, if not i can't shrink anyways due to the built in antenna :sob:)
i wanted the board to be at most pico size in length as the keyboard project doesn't give me much space to work with on the real estate aspect, hence the double row header design

2/19/2026 12 AM - my head hurts -- continued routing

gng i wish the title was all i needed to type but no journals have to be detailed

i kinda brought this upon myself
basically, continued routing, added footprints, made a mess of the 6 layers (thank goodness i have 6 layers)

will prob do some refactoring once i'm done to make good use of all 6 layers
for now i've been conserving the 5th layer (pink) unless it's absolutely necessary, but other layers r starting to fill up
kinda also screwed myself over with the chip placement
bc there's ofc gonna be more components on the top compared to the bottom of the pcb so top is super cramped while bottom is chilling
might be good for the RF though.. who knows

2/19/2026 6 PM - finished routing

guh

will def have to clean up some routing cause all the vias and layering are hella messy rn
but now the advice i've gotten are super conflicting
finished earlier last night / this morning at 1:24AM and posted about it in the blueprint channel
but was told the 6 layer w/ via in pad was unnecessary
but the advice i got to start the side project was only bc i was told to do 6 layers with free via-in-pad to avoid extra pcba and 4 layer design on the keyboard

FAHHH

anyways here's a slightly outdated screenshot of the route
the finished route is on a different laptop, only difference being 2 caps i forgot to finish placing last night

I was told that the 6 layers was fine for this case as long as i avoid it in the future as it can be hard to replicate the design if other people wanted to make it just because 6 layers with enig and all is expensive, if not for the JLC $2 deal

will also probs ask someone to sanity check the routing and everything before submit for design

2/22/2026 - reroute again and silkscreen + enig art :skull:

continued rerouting to clean up some excess vias, etc etc
i knew that the 6 layer came with enig but i just realized, if i make my own custom footprints, i can get enig plated art/lettering/whatever, so uh we ball
i added regular silkscreen to places where it's impossible to do copper text just because it looks weird blank, and moved lines where i can to fit the largest text and icons i can
overall looks pretty good
i'm pretty sure the bottom copper bluetooth symbol shouldn't affect the RF much because it's 5 layers down from the transmission, and the gnd surrounding it is relatively consistent

2/25/2026 - figuring out exports + fah

FAH again
i didnt realize that 4.7uF caps don't come in 0402 footprints
gpt lied :sob:

so now we gotta rework the board and re-export and reselect parts, lkasdjfl;ksdjfl;ksdajdflkdsajdfkladsjflkadsjsa

after 3 hotfixes we done bois

2/27/2026 - forgor battery

to simplify things i decided i would just add a battery connector, plus it up
however i also realized that it's probably a better idea to expose the out pin instead of the vbat pin
also added a bunch of decup caps to the out line, as well as security caps for other lines like 3v3

(pov skipping hw to work on this for 5 hrs)

3/1/2026 5 PM - more refinement + rendering

likely will be the final revision of the pcb, and will send off to production soon
thickened vbat traces and power traces in general, rerouted some stuff, added some more enig bc why not
here's the first render i did
bit low res but my laptop even though it's pretty good still renders this pretty slow

second render, higher res, without depth of field

3/1/2026 9 PM - bunch more rendering

technically not active development so im not gonna log too many hours
but yea, learned a bit more blender, settings etc to refine the render
i think ts looks absolutely sick

3/2/2026 - refinement + animation

another render i did
ts only took like 40 mins
also did some more small minor adjustments on the pcb, moving headers' footprints to back etc, it shouuuuld should be nearly done now regarding routing

animation

3/3/2026 - nvm

did another whole reroute
made the components sit more compact, made the gpios use less vias, etc etc minor improvements
plus more space for enig art :DDD


also added 2 tooling holes for jlc pcba bc i don't want them to drill in places i don't want or return mine bc they weren't able to find places

3/7/2026 6 PM - more rerouting + optimizing

rerouted a bunch of stuff and allowed the total track segment count to drop from 1.2k ish to less than 600

basically cut the amount of track data in half
spent really long deleting extra lines, small stubs inside pads that shouldn't be there, and fixed some curved lines that have been segmented by kicad into like 50 pieces each for some reason

3/7/2026 7 PM - fix DRC clearance errors and stuff

as title mentioned i fixed the via in pads on the inner layers to get rid of drc errors, also cleared out any errors with arc tracks' clearance with vias etc

3/9/2026 - decided to torture myself again

i decided that 1MB wasn't enough flash for most use cases that i might want so for safety I plan on adding a qspi flash to it
spent 3 hours last night looking for modules on jlc that has a small enough footprint and also the amount of storage I want, and also spent some time fixing fills and routing after a sanity check
64mbit can be in a 3x4 package but the amount I want is 128mbit/256mbit, which is only available at 5x6 and 6x8.. which the 5x6 can probably fit if i rearrange a bunch of stuff but 6x8 hail nah that's almost as big as the nrf by itself
also spent half an hour looking up if the qspi can be remapped to other pins other than the recommended pins bc i don't want to sacrafice my reset button/pin for spi
top two candidates rn for 16mB or 128mbit

and 256mbit /32MB

after i add this i will also have to reroute a bunch of lines and also add gnd and stuff bc qspi uses up 6 gpios, which helps and also doesn't help. it helps bc i want more gnd pins, but also i wanted as many gpios exposed as possible and this takes away 6

3/21/2026 - decided to un-torture myself

the size of storage i want is too big to reasonably fit onto the board so we taking a step back and going back to the orignal layout even tho i spent like 2 hours rerouting it and trying to fit the storage on :hs::::::::::

3/22/2026 - transferring to stasis! -- won't be submitting in bp

gbye blueprint
will finish in stasis for more rewards
ahhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh(this is here to fill up the char count requirement)